Multi-input, wide dynamic range bipolar and unipolar analog-to-digital converters (ADCs) have traditionally used resistor divider networks at the analog input to scale the input signal to the dynamic range of the converter before acquisition and conversion can take place. This method of attenuating the input signal prior to conversion by the ADC has been used very successfully in the past. However, it has a number of distinct disadvantages.
First of all, in the traditional resistor divider approach the analog input source always sees a resistive load to ground or some reference voltage. The source must be able to drive this load. Second, the resistor divider network consumes power both from the internal reference and from the analog input source. The third problem is that this prior art technique does not allow the user an easy method for programming the allowed analog input range. A fourth disadvantage is the fact that the size of the input resistors will limit the full power bandwidth of the converter.
The nodes of the resistor network that form the resistor divider can be made accessible to the user via pins on an integrated circuit (IC). The user then configures the resistor divider network via hardware connections to suit the analog input range required. However, if the user wishes to change the range, then the hardware has to be re-wired.
It is known in the prior art to construct an analog-to-digital converter integrated circuit using a process utilizing only 5 volt devices. This ADC is a successive approximation ADC implemented using a capacitor array DAC (CapDAC). The internal reference (Vref) is set at one-half the 5 volt supply voltage, or 2.5 volts. This particular device can accommodate two different input voltage ranges by sampling onto the full CapDAC for the 0 to Vref range, and half the array for the 0 to 2×Vref range. Of course, the maximum input voltage is limited to 5 volts. This device is available from Analog Devices, Inc. as their part number AD7866.
It has also been suggested that higher input voltages can be accommodated by fabricating the entire device using a high-voltage process. In the December 1975 IEEE Journal of Solid State Circuits, authors James L. McCreary and Paul R. Gray describe a SAR ADC fabricated entirely with a high-voltage process that can handle ±10 volt supplies. With the reference voltage set at 10 volts, the device can handle a 0 to 10 volt input voltage range by sampling onto its entire capacitor DAC array, and can thus accommodate an input voltage range from −10 volts to +10 volts by sampling onto just half of the CapDAC array. Presumably, the gate lengths for the devices described in this article are on the order of 6 microns, thus consuming considerable die area for a single device.
Consequently, a need arises for an analog input voltage scaling technique that is easily adaptable to integrated circuit applications, does not require the input signal to drive a resistive load to ground, minimizes power consumption, and is easily programmable in the event that the allowed analog input voltage range requires alteration.